PADS Designer Flows

IOD supports the following DxDesigner Flows:

• Schematic Export Flow for PADS Designer (FPGA First)

• Schematic Update Flow for PADS Designer (FPGA First)

• Schematic Update Flow for PADS Designer (PCB First)

Schematic Export Flow for PADS Designer (FPGA First)

The following steps describe how to create an FPGA component database in PADS I/O Designer, create and export symbols to DxDesigner, perform I/O planning and layout optimization using data from PADS Layout.

1. Create a new project containing a new FPGA database as described in “Creating a New Project” and “Adding Databases to a Board”.

2. Build the FPGA database either using the FPGA Database Wizard or by doing the following:

1. Select File > Database Properties and click the Vendor and Device page to specify an FPGA device. See Selecting the Device.

You can also specify FPGA vendor files such as Place and Route Constraints Files or Pin Report Files at this time. See “Importing FPGA Vendor Files”.

1. Select the Signal Source page to import I/O signals for the FPGA from an HDL file or spreadsheet. See “Defining I/O Signals”.

3. Set the I/O Standard for signals in the Properties Window. See “Set the I/O Standard”.

4. Add user-defined rules (optional step). See “User-defined Rules”.

5. Select Assign > Assign Pins or use the shortcut key F4 to assign signals to pins as defined in the HDL source specified. For information on other ways to assign pins, see Making Pin Assignments.

The pin assignments will follow device-specific rules as well as user-defined rules. See “Device-dependant Assignment Rules” and “User-defined Rules”.

The FPGA design is now ready to insert into the PCB schematic and go to Layout. The next step is to build a symbol set for the I/O signals and then export them to the schematic.

Note
	At this stage, the pin assignments are not optimized for the PCB layout.

6. Create symbols using the Symbols Generator. See “Symbols Generator”.

1. Invoke the Symbols Generator by selecting Symbol > Symbols Generator or by clicking the icon on the toolbar or at the top of the Symbol Window.

1. Create a hierarchical symbols for I/O pins.

This flow makes use of implicit power connections, so there is no need to create power and ground symbols. PADS I/O Designer will attach the necessary properties to the component.

7. Select Export > Schematic and Symbols to export the symbols to the schematic. See “Exporting Symbols and Schematics”.

8. In PADS Designer, run netlist generation and open PADS to view the optimized board results.

9. I/O Optimization (optional)

1. In the PADS I/O Designer layout database, select Import > Layout to load the PCB layout.

The PCB layout and netlines are visible in the Layout Window.

1. Review the layout and create new layout scenarios if further optimization is needed.

10. Select Export > Schematic and Symbols to update the schematic with the optimized pin assignments. See “Exporting Symbols and Schematics”.

If you specified FPGA vendor files when you set up the database, you can use the FPGA database’s Export menu to update them with the new pin outs. See “Place and Route Constraints Files” and “FPGA Xchange Files”. To create new files, select File > Database Properties and click the Place and Route page to enter file locations for these files.

With that step, the loop is completed and the FPGA design will be updated to reflect the optimized I/O assignments.

Schematic Update Flow for PADS Designer (FPGA First)

The following steps describe how to create an FPGA component database in PADS I/O Designer for use with Schematic Update to wire-up schematic components and optimize connections during layout creation.

1. Open the project in PADS Designer and place component symbols on the PADS Designer schematic.

2. To assign Ref Des, run Create Netlist for Layout or Assign Reference Designator (REFDES) in the PCB Interface.

3. Open the project in PADS I/O Designer.

4. Build an PADS I/O Designer database, including signals and pin assignments related to the component, from the schematic:

1. Use HDL and/or Pin Report File for the specific device.

1. Use spreadsheet file with signals and assignments.

5. Ensure proper PCB Part Number and Ref Des settings on the Database Properties - PCB Flow tab. (See “Database Properties Dialog Box”.) PCB Part Number and Ref Des are used to match components on the schematic.

6. Run Export - Schematic Update to wire-up the component symbols on the schematic according to assignments in PADS I/O Designer. Schematic update converts any signal name to a net name.

7. When the schematic update completes, perform forward annotation to PADS Layout and create layout.

8. Import the layout to the PADS I/O Designer FPGA database / layout database.

9. Optimize assignments using PADS I/O Designer's Unravel Nets functionality.

10. Run Export - Schematic Update to update net connections on the schematic according to the optimized assignments in PADS I/O Designer.

Schematic Update Flow for PADS Designer (PCB First)

The following steps describe how to create an FPGA component database in PADS I/O Designer for use with Schematic Update to optimize connections for a component which has already been placed on a PADS Designer schematic and used in the layout.

1. Open the existing project in PADS I/O Designer.

2. Build an PADS I/O Designer database, including signals and pin assignments related to the component, from the schematic:

1. Use the PCB Design Wizard option “Import signals and assignments only” to import signals and assignments into PADS I/O Designer from the schematic without importing the symbol.

1. Use HDL and/or Pin Report File for the specific device.

1. Use a spreadsheet file with signals and assignments.

3. Ensure proper PCB Part Number and Ref Des settings in Database Properties - PCB Flow tab. PCB Part Number and Ref Des are used to match components on the schematic.

4. Import the layout to the PADS I/O Designer FPGA database / layout database.

5. Optimize assignments using PADS I/O Designer's Unravel Nets functionality.

6. Run Export - Schematic Update to update net connections on the schematic according to the optimized assignments in PADS I/O Designer.