TCL read-only variable containing the name of the constraints file.
TCL read-only variable containing the name of the constraints file format.
TCL variable containing the file name of the current database.
TCL variable containing the directory name of the selected Design Architect project.
TCL variable containing the name of the selected device. This variable is read-only; to change device use the setpart command.
TCL variable containing the directory name of the selected DxDesigner project.
TCL variable containing the name of the selected family. This variable is read-only; to change family use the setpart command.
TCL read-only variable containing the name of the FPGA Xchange file.
TCL variable containing the name of the selected HDL file. This variable is read-only; to change an HDL file name use the setsourcefile command.
TCL variable containing the name of the selected package. This variable is read-only; to change the package use the setpart command.
TCL read-only variable containing the name of the pin report file.
TCL read-only variable containing the name of the pin report file format.
TCL variable containing the selected speed.
TCL variable containing the SSO Bank Threshold.
TCL variable containing the SSO Package Allowance.
TCL read-only variable containing the name of the synthesis constraints file.
TCL read-only variable containing the name of the synthesis constraints file format.
TCL variable containing the synthesis tool name.
TCL variable containing path to the timing report file.
TCL variable containing the timing report file format string.
TCL variable containing the name of the selected vendor. This variable is read-only; to change the vendor name use the setpart command.
TCL variable containing the Verilog search path.