Some I/O Standards require a VREF source with a specified value. If there’s a pin assigned with such an I/O Standard the VREF value is established for the entire bank.
In order to support vendor or custom rules, Xilinx DCI Cascading for example, PADS I/O Designer can also establish a VREF value across multiple banks.
PADS I/O Designer does not allow you to assign a different value to a pin than that required by the established VREF.