You can set PADS I/O Designer to automatically detect clock signals. To enable this functionality, select Setup > Settings + Advanced, then select Detect Clocks in the Clock autodetection section. PADS I/O Designer uses regular expressions to recognize lock signals. In most cases, clock signals are uniformly named, with names such as CLK. While parsing an HDL file, PADS I/O Designer looks for signals with similar names, and marks them as clock signals.
PADS I/O Designer can also recognize differential clock signals in an HDL design that has differential buffers instantiated in the top-level design. To enable this functionality, select Setup > Settings + Advanced, then select Recognize differential signals under HDL source section. PADS I/O Designer then sets DIFFCLOCK type on any detected differential clock signals.
You can modify clock assignments later, using the Type column in the Signal List. To mark or unmark a signal as a clock, locate it in the Signal List, click in the Type column, and select the CLOCK or IO option from the list. The clock property of a signal is stored in the database.