Name

Value

PCB Name

Signal PCB name

HDL Name

Signal HDL name

Dir

Indicates the direction of the signal (In/Out)

Pin

Shows the pin assigned to the signal

Type

Shows the type of signal

I/O Standard

Shows the I/O standard of the signal

Swap group

Shows the signal swap group

Locked by

Indicates whether the signal is locked

Symbol

Shows the symbol name that the signal is placed upon. If a signal is placed on more than one symbol, their names are separated by ‘&’.

STRENGTH

Shows the pin’s drive strength.

TERMINATION

SLEW_RATE

DELAY

Additional signal properties for Xilinx devices

WEAK_PULL_UP_RESISTOR

TREAT_BIDIR_AS_OUTPUT

SLOW_SLEW_RATE

POWER_UP_LEVEL

PCI_IO

INCREASE_DELAY_TO_OUTPUT_PIN

FAST_OUTPUT_REGSITER

FAST_OUTPUT_ENABLE_REGISTER

FAST_INPUT_REGISTER

ENABLE_BUS_HOLD_CIRCUITRY

DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS

STRENGTH

Additional signal properties for Altera devices