Table of Contents

Introduction to PADS I/O Designer

PADS I/O Designer Capabilities

PADS I/O Designer Integration

Settings Consolidation with PADS Designer

PADS I/O Designer Design Process

Licensing and Configuration

License Options

Environment Variables

User Definable Variables

Configuration File (IODesigner.xml)

Starting PADS I/O Designer

Starting PADS I/O Designer from Windows

Selecting a Scheme

PADS I/O Designer Workspace

Workspace Windows

Customizing Your Workspace

Selecting Objects

Copying Signal Data to the Clipboard

Copying Pin Data to the Clipboard

Printing Signals and Pins

Symbol Window Settings

TextEditor Window

DQ DQS Pins Display

DCI Cascade Region Display

Show Layout in Device View

Scrolling and Zooming in the Device Window

Quick Mouse Zoom Operations

Device Window Modes

Shortcuts in the Console Window

Properties Window

Signal Properties

Pin Properties for Layout Database

Port Properties

Symbol Properties

Graphic Properties

Text Properties

Synchronization Wizard

Synchronizing Files

Synchronization Check

GUI Startup Preferences

Errors and Warnings

Customizing Files and Directories

Changing the Appearance of Elements

Source Control Settings

Microsoft SourceSafe

Custom Source Control System

Advanced Settings

Typical Design Flows

Supported Schematic Design Creation Tools

PADS Designer Flows

Schematic Export Flow for PADS Designer (FPGA First)

Schematic Update Flow for PADS Designer (FPGA First)

Schematic Update Flow for PADS Designer (PCB First)

Working with Projects and Databases

What is a Project?

Opening a Project

Creating a New Project

Creating a Project in Cadence OrCAD® Flow

Adding a Board to a Project

Adding Databases to a Board

Viewing Settings

Adding an FPGA to the Design

FPGA Database Wizard

FPGA Device Setup

Selecting the Device

Importing FPGA Vendor Files

FPGA Device Library

Vendor Library Updates

FPGA Library Update Notifications

Preliminary Device Support

Design Rule Check

Defining I/O Signals

Importing I/O Signals Using HDL

Additional HDL Files

HDL Names and PCB Names

Importing I/O Signals Using a Spreadsheet

Creating and Editing Signals in the Signals List

Creating a New Signal or Signal Bus

Removing Signals

Renaming Signals

Combining Signals into a Bus Signal

Differential Pairs

PCB Signal Assignments

Set the I/O Standard

Design for Multiple Devices in a Common Package

PCB Design Wizard

User-defined Rules

Creating a New Rule

Making Pin Assignments

Assigning Signals to Pins

Assigning Signals to Pins Using Drag and Drop

Changing Assignments in Lists

Choosing Signals/Pins to Assign from a List

Combining Pins into a Bus Pin

Pin and Signal Types

Clock Assignments

Differential Pins Support

Multi-Gigabit Transceiver Pins

Special Signal/Pin Assignments

Setting Types Compatibilities

Making Special Assignments

Creating, Editing and Updating Symbols and Schematics

Symbol Generation

Symbols Generator

Creating a New Symbol Using the Symbols Generator

Updating Symbols Using the Symbols Generator

Updating Symbols in Databases Created Using Older Versions of PADS I/O Designer

Power Symbol Generation

Explicit Power Connection Symbols

Configuration Symbol Generation

Update Power Signals

Building a New Symbol

Port Types and Shapes

Adding an Image to a Symbol

Editing Symbol Elements

Moving and Changing Elements

Changing Symbol Backgrounds

Printing Symbols

Deleting Symbols

Symbol Editor Settings

PCB Signals Generation

Symbol Export Settings

Creating Generic Symbols for Use With PADS I/O Designer

Importing Symbols from Independent Libraries

Exporting Symbols and Schematics

Hierarchical Schematic Generation

Flat Schematic Generation

Placing Symbols in an PADS Designer Schematic

Importing Symbols and Schematics

Schematic Update

Additional Information

Optimizing the I/O Assignments

I/O Optimization Methods

Fan-out Visibility

Layout Database

I/O Optimization

Synchronizing the Layout Database with a Design

Select Pin/Net Mode

Connectivity List Window

Adjusting Component Orientation

Unraveling Procedure

Unravel All FPGAs

Layout Scenarios Window

Creating and Applying a Layout Scenario

Multi-chip PCB Optimization

HDL and EDIF/XML Files

Recognizing Differential Signals

Synthesis Constraints Files

Place and Route Tools

Place and Route Constraints Files

Pin Report Files

FPGA Xchange Files

FPGA Device Library Path

Timing Report Files

Design Rule Check for Altera Devices

Automatic SSO Check

Generating Device List

Exporting Symbols to a Library

Integration with PADS Designer

Importing an Existing PADS Designer Project

Importing Symbols from PADS Designer

Exporting Symbols/Schematics to PADS Designer

What is Exported to PADS Designer?

Updating Symbols/Schematics from PADS Designer

What is Updated from PADS Designer?

PADS Designer Usage Scenarios

Scenario 1: PADS I/O Designer Normal Mode - PADS Designer

Scenario 2: PADS I/O Designer with Existing Symbols with PCB Mapping Data - PADS Designer

Scenario 3: PADS I/O Designer with Existing Symbols (Schematic Update)

Using the Interconnectivity Table Editor

Integration with Pads Layout

Constraints Bus Members Generation

FPGA Updater Introduction

Manually Launching FPGA Updater

Automatically Launching FPGA Updater

Checking for Updates

Critical Release Update

Downloading Updates

Backup of Current FPGA Library

FPGA Updater Log Viewer

Backup and Rollback of FPGA Library.

Updating FPGA Libraries in a High Security Design Environment

PADS I/O Designer Tool Reference

Navigating List Windows

Operations on Columns

Filtering to Selected Rows

Wildcard Filters

Regular Expression Filters

Creating Custom Filters

Changing the Pin Name Font Size

Keyboard Shortcuts

Global Shortcuts

Shortcuts in Signal and Pins Lists

Shortcuts in the Symbol Window

Shortcuts in the Device Window

Managing Keyboard Shortcuts

Modifying Shortcuts

Active Keyboard Shortcuts View

Layout View Toolbar

Unravel Toolbar

Source Control Toolbar

Creating and Running TCL Scripts

PADS I/O Designer TCL Commands

addexternalfile

addignorelengthnet

addportwithlabel

addportwithlabelandedit

changeattribvisibility

changebuspinrange

changelabelvisibility

delinstanceattrib

export_all_schematics

exportbackground

exportschematic

generate_constraints_file

generate_fpga_xchange_file

generatesymbols

generate_synthesis_constraints_file

gettracksyncstatus

importlmcsymbol

invertbussignals

prjaddexistingdb

scalebackground

sccreateproject

scgetlatestversion

schematicupdate_all

screfreshstatus

set_constraints_file

set_design_architect_project

set_dx_designer_project

set_expedition_layout

set_fpga_xchange_file

set_pin_report_file

set_synthesis_constraints_file

set_timing_report_file

setbackgroundproperty

setdefaultlinestyle

setdefaultoutline

setfunctionalblock

setinstanceattrib

setoutlinecolor

setsimilardevices

settracksyncstatus

typescompatibility

update_from_constraints_file

update_from_fpga_xchange_file

update_from_pin_report_file

update_from_synthesis_constraints_file

updatepowersignals

update_symbols_attributes

PADS I/O Designer Defined Scalar TCL Variables

constraints_file

constraints_file_format

ddp_project_path

dx_project_path

fpga_xchange_file

pin_report_file

pin_report_file_format

sso_bank_threshold

sso_package_allowance

synthesis_constraints_file

synthesis_constraints_file_format

timing_report_file

timing_report_file_format

verilog_search_path

PADS I/O Designer Defined TCL Array Variables

Design Versioning

Source Control Configuration

Source Control Usage

Getting Existing Databases

Adding Databases to the Repository

Additional Files in the Repository

Getting Latest Database Version

Checking Out the Database

Checking In the Database

Browse Changes History

Showing Differences

Refreshing Source Control Status

Dialog Boxes and Field Reference

Settings Dialog Box

Database Properties Dialog Box

Layout Database Properties Dialog Box

Add Signal Dialog Box

Edit Primitive Value(s) Dialog Box

Import Design Wizard Dialog Box

xDX IOD Components Dialog Box

Library Components Dialog Box

Rule Editor Dialog Box

Unravel Nets Dialog Box

External Tools Dialog

Preferred Devices List

Vendor Support Information

Device-dependant Assignment Rules

Actel Assignment Rules

Altera Assignment Rules

I/O Pin Placement with Respect to LVDS I/O Pins

Xilinx Assignment Rules

Lattice Assignment Rules

Generic IO Standards

Third-Party Information

End-User License Agreement with EDA Software Supplemental Terms