PADS I/O Designer Integration

PADS I/O Designer generates Place & Route constraints, based on the HDL design and mapping process and then allows you to create the necessary symbols, schematics and hierarchical associations based on the “post-route” pin data.

PADS I/O Designer allows you to:

• Read signals from entities in VHDL files, and modules in Verilog files.

• Define signals within the PADS I/O Designer environment, and generate VHDL entities, or Verilog modules.

• Import/export CSV files.

• Choose an FPGA device from devices supported by vendors such as Xilinx, Altera, Lattice or Actel.

• Map HDL signals to FPGA pins, and generate FPGA constraints.

• Update mappings based on the files generated by Place & Route software.

• Create and edit functional-level, and board-level symbols in the advanced built-in Symbol Editor.

• Generate symbols and schematics.

• Work in teams through the built-in version control systems interface.

• Optimize I/O pin assignments improving efficiency on the PCB and drastically reducing design time.

PADS I/O Designer does not run in standalone mode. It is used in conjunction with other design solutions such as PADS Designer.

Settings Consolidation with PADS Designer

When you are using PADS I/O Designer with PADS Designer, PADS I/O Designer derives settings from both PADS I/O Designer and PADS Designer, as follows:

• PADS I/O Designer reads grid and object styles from DxDesigner.xml, and does not change them.

• PADS I/O Designer reads PADS I/O Designer-only settings from several PADS I/O Designer files, in the following order:

• iod.xml - in the installation directory /<mgc_home>/<release>/SDD_HOME/IODesigner/resources/iod.xml.

• IODesigner.xml - in the corporate working directory (WDIR), if the file exists.

• IODesigner.xml - in the user working directory (WDIR).

PADS I/O Designer saves settings only to the IODesigner.xml file in the user working directory.

PADS I/O Designer Design Process

PADS I/O Designer takes its initial settings from a default set in the iod.xml file in the installation directory. PADS I/O Designer then reads in your company's more specific settings, and where there are differences, the last read settings win. PADS I/O Designer then reads the user's IODesigner.xml file for environment specific settings. Finally, PADS I/O Designer reads your schematic design tool's .xml files to ensure PADS I/O Designer output has a matching look and feel for the schematic environment. See the reference guide for your schematic design tool for more detail about schematic settings.

The initial FPGA signals and/or assignments are typically imported by PADS I/O Designer from the FPGA vendor tools (for example, Actel, Altera, Lattice, Xilinx). After the PCB process integration and I/O optimization, the new signal assignments are exported to the respective FPGA vendor tool. PADS I/O Designer is knowledgeable of the FPGA vendor specific file formats making data movement very easy.

PADS I/O Designer starts by importing a signal list in the form of an HDL file or an FPGA vendor netlist. The signals may or may not be assigned at this point. I/O assignment can be easily done in a correct by construction fashion within PADS I/O Designer. PADS I/O Designer provides a device library that incorporates most of the vendor-specific pin assignment rules. The benefit comes from having the ability to assign and optimize pin assignments in the PCB design process.

Once an initial pin assignment is made, PADS I/O Designer is used to generate a symbol set for the FPGA. Symbols can be fractured based on a number of different parameters. The symbol set along with the schematic can be exported directly to the schematic tool. The benefit comes from automating two manually intensive activities - symbol and schematic creation.

After a preliminary PCB layout is complete , PADS I/O Designer can import the layout to begin the I/O optimization phase. You can view the actual component orientation and netlines as it appears in the layout tool. The goal is to use PADS I/O Designer to optimize the pin assignment for this particular component orientation. This is done by moving pin assignments to shorten netlines and remove cross-overs. Once you feel that this is the best I/O assignment for this component orientation, PADS I/O Designer will update the symbols and schematics to reflect the new pin assignments. The quality of the PCB is dramatically improved based on the optimized I/O assignment in the form of fewer layers, shorter traces, less vias and as a derivative improved signal integrity. This also lowers PCB costs.