Use this dialog box to set information for the database.
The available contents differ depending on the type of database: FPGA (.fpc) or layout (.lpc).
To access the FPGA properties dialog box, click File > Database Properties, and click the appropriate page from the list. (You can change the active FPGA by double-clicking it from the Project Window.)
Table 16-3.
FPGA Properties Dialog Box
Field
Description
Vendor and Device
Vendor
Specifies the device Vendor:
Actel
Altera
Lattice
Xilinx
Tool
Specifies the tool or library from which the device originates
Family
Specifies the family of devices
Device
Specifies the device itself
Package
Specifies the package for the device
Speed
Specifies the speed at which the device runs
Default single
Specifies the default I/O standard for single signals.
Default differential
Specifies the default I/O standard for differential signals.
Signals Source
Signals source
Specifies the format of the source signals file: VHDL, Verilog, or Spreadsheet.
File Path
Specifies the path to the source data file.
Browse
Opens a Browse window to navigate to the source file.
More
Opens the Settings dialog to show related signals settings.
VHDL definition (active when the signals source is VHDL)
VHDL File
Specifies the path to the VHDL file.
Entity
Specifies the entity from the source data to use.
Additional VHDL files
Specifies additional VHDL files to use.
Verilog definition (active when the signals source is Verilog)
Verilog File
Specifies the path to the Verilog file.
Module
Specifies the module from the source data to use.
Verilog search paths
Specifies additional Verilog files to use.
Spreadsheet definition (active when the signals source is Spreadsheet)
Spreadsheet File
Specifies the path to the spreadsheet file.
Delimiter
Specifies the delimiter used in the imported data.
Attributes
Specifies the signal attribute order to use in the spreadsheet.
File preview
Displays a preview of the data.
Place and Route
Constraints file name
Specifies a Place and Route constraints file.
Pin report file name
Specifies a Place and Route pin report file.
Timing report file name
Specifies a Place and Route timing report file.
FPGAX file name
Specifies an FPGAX file.
Synthesis
Tool name
Specifies the Synthesis tool used:
Leonardo Spectrum
Precision
Synopsys
Synplify Pro
Xilinx Synthesis
Constraints file
Specifies a Synthesis constraints file.
PCB Flow
Part number
Allows you to enter a PCB Part Number.
Cell name
Allows you to enter a PCB cell name.
Ref Des
Allows you to enter a Reference Designator for the device.