Integration with Pads Layout
PADS I/O Designer reads the PCB layout information contained in the Pads Layout layout file. This allows you to view the connections between the current device and the surrounding elements on the PCB schematic.
Figure 11-4.
PADS Designer + PADS
Figure 11-5.
Cadence OrCAD + PADS
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PADS I/O Designer does not export default I/O standards to Constraint Manager. You must explicitly set signal I/O standards to export the standards to Constraint Manager. |
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During schematic export, PADS I/O Designer recreates the schematic with related FPGA components so that the PADS I/O Designer connectivity changes are transferred to PADS Designer. To preserve Constraint Manager data:
- When optimization is performed in layout context (layout imported to PADS I/O Designer) you must first import the schematic changes to the FPGA database (RefDes) as prompted by the synchronization wizard. You must synchronize the FPGA database with PADS Designer before performing assignment changes, or Constraint Manager data for the FPGA related nets can be lost.
- When assignments are changed in PADS I/O Designer without layout context (for instance, import of FPGA constraints file, pin report file, and so on), you must first synchronize the PADS I/O Designer FPGA database with the PADS Designer schematic (RefDes imported), as prompted by the synchronization wizard.