PADS Designer Usage Scenarios

This section details the use of PADS I/O Designer in a PADS Designer flow. The section covers three possible usage models:

Full flexibility mode where PADS I/O Designer is used to generate symbols/fractures, schematics and the PCB pin-swap data for layout. The advantage of using this flow is the unconstrained PCB layout optimization ability.

This is the most restricted mode. It uses existing schematic symbols and the associated PCB mapping data from the symbol library. PADS I/O Designer is used to generate the schematics but there is no swap information exported to the symbols during the export process. In this case, the data must match the PCB mapping data from the library. Using this method limits the ability to optimize the PCB layout to PADS I/O Designer capabilities. The only way to do it is by using PADS I/O Designer’s Multi-Component View feature.

This usage model provides the most design structure flexibility. It supports both flat and hierarchical design structures, and divides the design process along traditional team boundaries (librarian, PCB functional designer, PCB physical designer) in alignment with historical design practices. It has the advantage that the FPGA is seen by the PCB as a normal component in your library.

Scenario 1: PADS I/O Designer Normal Mode - PADS Designer

In this mode of operation PADS I/O Designer creates both the symbol data and the PCB mapping data for the design. This allows the greatest level of flexibility when optimizing I/O and allows for fast iteration through the design process. The schematics and symbols are generated by PADS I/O Designer and are simply forward annotated to the PCB design. The process is shown in the flowchart below followed by the steps for this flow.

Figure 11-1. PADS I/O Designer Normal Mode - PADS Designer

After mapping the signal names to the appropriate pins in the device, the Symbols Generator can be used to quickly generate the PCB level symbols and PCB data ready for layout. To launch the Symbols Generator, click the icon on the toolbar or choose Symbol > Symbols Generator from the menu.
For a detailed description of the Symbols Generator, see the section called “Symbols Generator”.

The symbol may be fractured according to one of the schemes supported by PADS I/O Designer or created as a custom fracture set.

PADS I/O Designer will then generate the required symbols and schematics during the export process, along with a design specific set of pinswap attributes. To export schematics and symbols, use the Export > Schematic and Symbols menu entry.

The design is now ready to forward annotate to your PCB design tool.

Scenario 2: PADS I/O Designer with Existing Symbols with PCB Mapping Data - PADS Designer

In this mode of operation PADS I/O Designer uses a set of library data from the symbol library including the PCB mapping data for the existing schematic set. This limits the capability to perform optimization during layout using the PCB tools as the PDB entry in the symbol library will probably not contain any pin-swap information. The process is shown in the flowchart below followed by the steps for this flow.

Figure 11-2. PADS I/O Designer with Existing Symbols and PCB Mapping Data

PADS I/O Designer can import a set of existing symbols and use it to map the pin to signal assignment of the device to the generated schematics. PADS I/O Designer can import from a project file, schematic file or library using the Import > Symbols from Board menu item.

Once the symbols are available they can be imported into PADS I/O Designer. In order to associate the symbols with the correct schematic it is necessary to have the top-level functional symbol created in PADS I/O Designer; If it does not exist, then the imported symbols will not have an associated functional block. The functional block can be generated as soon as the HDL definition has been loaded into PADS I/O Designer.

The PCB Symbol check box should be set. Make also sure that the Readonly symbol option is checked this time since this will fix the swapping ability that is read from library symbols, and therefore fix the swapping to the way it is defined in the symbol library. Setting the Read-only symbol option also gives the DEVICE attribute a correct value that matches the part number in the symbol library, which causes the pin numbers and mapping data to be taken from the symbol library PDB during netlist generation. Once the symbols are imported, PADS I/O Designer will map signal associations to the symbols.

After the symbols have been imported and the assignment completed the schematics must be generated using the Export > Schematic and Symbols menu. PADS I/O Designer generates the schematic for the device complete with the correct connectivity.

The design then forward annotates to layout using the entries in the symbol library. Pin swapping will not be available in the PCB design tool, but you can use the device window and layout view in PADS I/O Designer to achieve optimization.

Scenario 3: PADS I/O Designer with Existing Symbols (Schematic Update)

In this mode of operation, supporting both flat and hierarchical design structures, PADS I/O Designer simply updates the connectivity of the schematic. This flow style divides the design process along traditional team boundaries: Component Librarian, PCB Functional Designer, PCB Physical designer aligning with traditional design practices, so PADS I/O Designer usage in this mode is simpler from both a learning perspective and a command set perspective. The process is shown in the flowchart below followed by a description of this flow.

Figure 11-3. PADS I/O Designer with Existing Symbols (Schematic Update)

FPGA Symbols and the PDB are normally placed in the symbol library and re-used across multiple PCB projects. Symbols and the PDB can also be used locally, within the project. The FPGA (as seen by the PCB) is a normal component in your library, just like any other component you use on your PCB. xDM Library supports FPGA components, since they are seen as normal PCB components.

FPGA Symbols are manually instantiated into the design, just like any other component in the design and can be mixed with any other components on the same schematic sheet. The update process updates the connectivity but does not re-generate the schematic, so your edits are never lost.