Place and Route Constraints Files

Constraints files pass data such as pin assignments from PADS I/O Designer to the Place & Route tool. To generate a Place & Route constraints file from PADS I/O Designer, select Export > P&R Constraints File. Constraints files formats vary between vendors. Below is the list of Vendor - Constraints file formats.

Actel (.pin, .gcf or .pdc)

Altera (.csf or .qsf)

Caution
	If you use the XSTL_INPUT_ALLOW_SE_BUFFER option in a QSF file, the QSF file must be imported before the PIN file so that all assignments are imported properly.

Xilinx (.ucf)

Lattice (.lpf)

PADS I/O Designer monitors Place & Route constraints files using the Synchronization Wizard, but they are not selected for update by default. During the constraints file generation process, PADS I/O Designer writes necessary information such as pin assignments, I/O Standards and the target device, to the constraints file. It does not overwrite any other information present in the file. Therefore, it is safe to have a constraints file created in an external program, load the file into PADS I/O Designer, modify it, and then save your changes by selecting Export > P&R Constraints File.

Note
	It is important to save the FPGA database following an import of constraints files (.lpf) or pin report files (.pad) from Lattice. This ensures that the correct bus syntax is applied to all bus members.