Place and Route Tools

PADS I/O Designer allows you to read in a Place & Route constraints file or Pin Report file, change pin assignments, and regenerate the constraints file to be read by the Place & Route software. PADS I/O Designer supports reading and writing constraints files for the following Place & Route tools:

Libero 11.1 / Actel Designer 10.0 / Actel Designer 9.1 / Actel Designer 9.0 SP2

Altera Quartus II 13.0 / Altera Quartus II 12.1 / Altera Quartus II 9.0 SP2

Lattice Diamond 2.2 / Lattice ispLEVER 8.1

Libero 11.1 / Designer 10.0

Xilinx ISE 14.4 / Xilinx ISE 14.6 / Xilinx ISE 14.7 / Xilinx Vivado 2012.4 / Xilinx Vivado 2013.2 / Xilinx Vivado 2013.3 / Xilinx ISE 10.1 SP3

Note
	PADS I/O Designer supports older FPGA tool versions but these are not included in the standard installation: Actel Designer 8.6 SP1 / 8.5 SP2 / 8.4 SP2 / 8.3 SP1 / 8.2 SP2 / 8.1 SP2 / 8.0 SP2 / 7.3 SP2 / 7.2 SP2 / 7.1 / 7.0 SP1 / 6.3 /6.2 SP2 / 6.1 SP1 / 6.0 SP2 / 5.2 SP1 / 5.0 SP1 Altera Quartus II 10.1 / 10.0 SP1 / 9.1 SP2 / 8.0 SP1 / 7.2 SP3 / 7.1 SP1 / 7.0 / 6.1 / 6.0 SP1 / 5.1 SP2 / 5.0 SP2 / 4.2 SP1 / 4.1 SP2 / 4.0 SP1 / 3.0 SP2, MaxPlus II 10 Lattice ispLEVER 8.0 / 7.2 SP2 / 7.2 SP2 / 7.1 SP1 / 7.0 SP2 / 6.1 SP2 / 6.0 SP1 / 5.1 SP2 / 5.0 SP1 Xilinx ISE 14.3 / 14.2 / 14.1 / 13.1 / 12.4 / 12.3 / 12.2 / 12.1 / 11.5 / 11.4 / 11.3 / 11.2 / 11.1 / 9.2 SP4 / 9.1 SP3 / 8.2 SP3 / 8.1 SP3 / 7.1 SP1 / 6.3 SP3 / 6.2 SP3 / 6.1 SP3 These libraries can be provided upon request.