HDL and EDIF/XML Files

PADS I/O Designer allows you to work with HDL files in the following way:

• Read signals from an HDL/Netlist file, see “Importing I/O Signals Using HDL”.

• Create signals and let PADS I/O Designer generate an HDL/Netlist file

• Update signals from an HDL/Netlist file

To generate an initial VHDL entity or Verilog module from PADS I/O Designer, select Export > VHDL Entity or Export > Verilog Module. Only ports in entity/module declaration are generated, without any underlying architecture. This allows manual addition of signals within PADS I/O Designer (see the section called Adding, removing, and renaming signals). Subsequently an HDL file is generated as a starting point for further design, that is, writing architecture/module contents.

PADS I/O Designer monitors HDL files using the Synchronization Wizard. Whenever the HDL file is changed and the ports of the unit displayed in the Signals List are modified, the Signal List is updated to reflect the actual unit declaration.