Schematic update allows the exporting of assignment changes to the schematic tool without changing any symbols. All changes are implemented by updating the connectivity between existing symbols. This section provides some additional information with regard to the process.
Schematic update displays a dialog that indicates elapsed time as the process runs.
Schematic update reports all unassigned signals at invocation to let you know that some pins will not be connected on the schematic. If you intentionally left the signals unassigned, you can ignore the warning and proceed to update the schematic.
If there are missing pins in the schematic, the schematic update process stops, and an error message displays directing you to the UpdateSchematic.log for a list of missing pins.
When schematic update completes without errors, PADS I/O Designer immediately saves all files.
Schematic update works only on nets connected to symbols describing the FPGA component on the schematic. The component is matched by the RefDes and Part Number attributes if they are specified in PADS I/O Designer. If RefDes is not specified, the part number is used. Either one of these attributes must be specified for schematic update to match any component on the schematic.
Schematic update converts any signal name to a net name. For plain signals, this conversion does not change anything. For buses, PADS I/O Designer angle brackets are replaced with round or square brackets, or nothing, according to Net Name Delimiter setting in PADS Designer.
When schematic update finds that a net connected to a given pin number has a different name to the one generated from the signal, a net is updated. The segment of the original net, which is connected to FPGA symbol, is cut from this pin. The new stub net is created with the right net. If the original net is already a net stub, it is not cut but its name is updated instead.
Updating schematics created by the user: In order for schematic update to work correctly in this use-case, all PADS I/O Designer signals must have the same names as the nets connected to symbols representing the FPGA device on the schematic. This condition can be met by generating a signal list using the import PCB design wizard in PADS I/O Designer, an HDL file, or a spreadsheet file. If the signal source is different, you must validate that the signal names match.
Another requirement is that symbols matching the PADS I/O Designer component should have the same set of pin numbers as the FPGA device. Pins existing only in the symbols will not be updated. If some pins exist only on the FPGA device, no nets for their signals are generated on the schematic, and an error message displays directing you to the UpdateSchematic.log for a list of missing pins.
Updating schematics generated by PADS I/O Designer: Schematic update can be used to update PADS I/O Designer generated schematics. In this case, only the nets connected to PCB symbols are updated, as functional symbols have no pin number attribute.