Power Symbol Generation
FPGA power can be managed as implicit connections in the PDB or explicitly in the generated symbols.
A list of default power signal name assignments can be viewed under Setup > Settings + PCB signals generation.
If an I/O Standard is not selected with a specific voltage (for example, 2.5, 3.3, 1.8 volts) the top window on the dialog is ignored and the power signal names shown in the bottom window are used. If an I/O Standard is selected (for example, LVCDI_33), PADS I/O Designer will detect a 3.3 volt signal and apply the Default PCB Signal in the top window named ‘v_3_3’. PADS I/O Designer will automatically configure the Bank where this pin resides.
Explicit Power Connection Symbols
Explicit power management requires the generation of power symbols. By selecting power symbol creation in the Symbols Generator, PADS I/O Designer automatically creates new power signals in the Signals List. New power signals are automatically assigned to the correct power pins in the Pins List.
Power signals are not part of the functional block that is created as part of the Symbols Generator process. But power symbols are exported as part of the Exporting Symbols and Schematics step. Power symbols must be placed and the proper power and ground signals must be manually attached.
PADS I/O Designer will automatically create new power signals based on the I/O Standard assignment and makes the appropriate assignments for the bank VCCO pins. In Figure 9-2, the P_DATA bus was assigned a LVCMOS25 standard which requires a 2.5V VCCO supply. PADS I/O Designer automatically creates the signal during symbol generation and makes the assignments.
Figure 9-2.
Power Signal Generation Based on I/O Standard Assignment
Configuration Symbol Generation
The Symbols Generator may be used to create configuration symbols such as JTAG by checking the CONFIG Pins group in the Symbol Settings page. When you complete the Symbols Generator, this creates symbols for all the pins with type CONFIG (except Vrp and Vrn which are put onto the Vref pins symbol).
If more control is required, CONFIG signals can be added and the symbol created manually. To do this, use the following steps:
- After the JTAG signals are added to the FPGA database, assign them to the JTAG pins by dragging the JTAG pin to the JTAG signal.
- Create a new empty symbol by selecting Symbol > New or by clicking the
icon on the toolbar or on the Symbol Window.
- Manually create the symbol by dragging the pins from the Pins List to the new symbol in the Symbol Window. The result is a symbol specifically for JTAG purposes.
Figure 9-3.
Manually Created JTAG Symbol
The JTAG symbol is typically not part of the hierarchical block. Make sure the Symbol Properties do not list a functional block attribute.
This symbol can now be exported and placed in the schematic. See "Exporting Symbols and Schematics".
Update Power Signals
The Update Power Signals functionality (Tools > Update Power Signals) checks the correctness of GND, VCC, VCCO, VREF, VRN, and VRP pin assignments. In the case of VCCO and VREF pins, PADS I/O Designer checks whether or not all pins are connected to the correct voltage levels. It also checks if other power pins are connected.
Checking power signals involves setting up GND, VCC signals to power the device and VREF and VCCO signals to set thresholds for I/O standards used in the device. There are also VRN and VRP pin connections that are necessary to set up DCI I/O standards. To ensure signal integrity before creating symbols, update power signals is run automatically (if not disabled) before every:
- Schematic Update / Schematic Update for All Components
- Export Schematic and Symbols / Export Schematic and Symbols for All components
- Export All Symbols / Export Current Symbol Only
- Export Interconnectivity Table / Export Interconnectivity Table for All Components
Update Power Signals creates power signals from the information in the Pins window’s VCCIO and VREF columns. PADS I/O Designer fills these columns automatically, taking into consideration signal I/O standards and direction.
In the event that power signals are not assigned correctly, PADS I/O Designer suggests the correct assignments as shown in Figure 9-4. You can then choose to Apply or Discard the suggested assignments using the buttons on the dialog. Select “Disable checking PCB signals again” to disable automatic checking. If you disable automatic checking, you can still manually check PCB signals by selecting Tools > Update power signals.
