Unravel Nets

Unravel Nets optimizes signal to pin assignments by shortening nets and eliminating crossovers on the PCB or layout. This allows much more efficient routing of nets in the physical design tool. The following sections describe unraveling nets:

Note

I/O Designer does not perform automated pin swapping on Multi-Gigabit Transceivers (MGT) signal types due to implementation specific pin placement considerations.

 

Unraveling Procedure

Use the following procedure to perform unraveling:

  1. In the Layout Window, select the component and / or nets, and either right-click and select Unravel Nets, or click the unravel button to open the Unravel Nets Dialog.

Figure 10-5. Unravel Nets Dialog

  1. Check Unravel scalars and buses concurrently in order to use all signals selected for unravel as one package of nets and pins (optional).

When this option is checked, all signals selected for unravel are used as one package of nets and pins, allowing, for example, a scalar net to be swapped with one of the bits of a bus. When this option is not checked, bus members are unraveled separately within the bus, and scalar nets are unraveled with other scalar nets.

  1. Check Use unused pins to include unoccupied pins in the unraveling process (optional).

When this option is not checked, the unravel process uses only the currently occupied pins, resulting in a set of swaps made on signals. When this option is checked, the algorithm uses both the currently used pins and the unassigned pins, allowing much more flexibility in finding optimal results.

  1. Click Unravel to begin the unraveling process with the current options.

Any user-defined rules set for the device are taken into account during unraveling. All signals marked as Locked in the Signals List are not moved during unravel process

Select the Cancel button at any time during the process to stop unraveling.

  1. Click Close to save the current unravel settings and exit the dialog.

Figure 10-6 and Figure 10-7 show examples of nets before and after unraveling.

Figure 10-6. FPGA Nets Prior to Unraveling

Figure 10-7. FPGA Nets After Unraveling

Unravel All FPGAs

The Edit > Unravel Nets > Unravel All FPGAs menu selection unravels all FPGAs in one step. A progress bar tracks progress of the unraveling.