I/O Optimization

I/O Optimization is defined as utilizing the actual layout data to optimize the I/O. The step requires a PCB layout.

In PADS I/O Designer, the layout database can be populated from the PADS physical layout using Import > Layout.

Now, the I/O can be further optimized, new layout scenarios can be created and applied.

When loading a board from PADS, you can view the netlines from a pin-to-pin view or a pin to partial route view. This can be valuable when considering I/O alignment with a large bus. A pin-to-pin view may leave unwanted cross-overs based on routes that are already in place.

Note

Partial route traces and breakouts are taken into account during unraveling.

In Allegro flow, PADS I/O Designer does not show traces on the layout, so only unravel from pins is performed.