Creating and Editing Signals in the Signals List

In an FPGA database, signals can be added, removed and renamed in the Signals List using the Add Signal dialog.

Creating a New Signal or Signal Bus

Use the following procedure to create a new signal and add it to a database in the Signals List:

  1. Do one of the following to display the Add Signal dialog:
  1. Right-click in the Signals List and select Add Signal...
  1. Select the menu item Edit > Add Signal...
  1. Enter a name for the signal in the Name field.
Caution

Signal names must not start with a hyphen (-) and cannot contain any of the following characters: square brackets ([ ]), parentheses (( )), angle brackets (< >), commas (,), tabs, or spaces.

 
  1. Select the signal’s direction (In, Out, Inout, Buffer or Linkage) in the Direction field.
  1. Select the signal’s type in the Type field.
  1. Enter an I/O standard if you don’t want the default value.
  1. Specify a range of values in order to create a signal bus (optional).

Removing Signals

Use the following procedure to remove a signal from a database:

  1. From the Signals List, select the signal or signals to be removed and do one of the following:

The signal(s) will be removed from the Signals List.

Renaming Signals

To change the name of a signal in a database, use the following procedure:

Caution

Signal names must not start with a hyphen (-) and cannot contain any of the following characters: square brackets ([ ]), parentheses (( )), angle brackets (< >), commas (,), tabs, or spaces.

 
  1. From the Signals List, select the signal to be renamed and do one of the following:

Combining Signals into a Bus Signal

In the Signals List, signals can be grouped into buses, known as bus signals. Bus signals are created automatically for vectors read from an HDL file. Additionally, user-defined bus signals may be created at any time. To create a bus, use the following procedure:

  1. In the Signals List, select the signals which will form the bus.
  1. Right-click on the selection and select Combine.
  1. Enter a PCB name and an HDL name for the bus signal. Optionally, you can use the controls on this dialog to adjust the range of signals in your bus.

A bus signal is created and can be identified in the Signals List by the plus sign at the left of the bus name.

Click the plus sign to expand or collapse the bus in the list, displaying or hiding its elements. Alternatively, select View > Expand, or View > Collapse to do the same thing. To expand or collapse all buses together, select View > Expand All, or View > Collapse All.

Note

Buses cannot be nested - bus signals cannot be combined into another bus.

 

A bus can be split or replaced with the flat list of its elements. To split a bus right-click on it and select Split. To split all buses at once, right-click in the List Window and select Split All.

Bus signals can be renamed in the same way as other signals. See "Renaming Signals".

Related Topics

Differential Pairs

To create a differential signal pair from existing signals, select the required signals in the Signals List, right-click and choose Create Differential Pair.

To split a differential pair back into separate signals, right-click the selection and choose Split Differential Pair.

When adding signals to the Signals List manually, you can specify that they are a differential signal pair by selecting the signal type as DIFF in the Type field on the Add Signal dialog.

In an FPGA database, differential signal assignments assign the whole DIFF signal, and member assignment is done automatically.

Differential signals are displayed as shown in Figure 6-2.

Figure 6-2. Differential Pairs Displayed in the Signals Window

PCB Signal Assignments

PADS I/O Designer supports PCB signal assignments. Special signals, for example ANALOG_GND, may be assigned to pins from the PCB page of the Pins List. PADS I/O Designer allows you to add and use PCB signals directly in the Signals List. You can distinguish HDL signals from PCB signals by their icons.

For automatic PCB Signal assignment, you can use Update Power Signals.

Set the I/O Standard

FPGAs are very flexible and PADS I/O Designer fully supports the variety of I/O standards available. To change a signal’s I/O standard (IOS), select the signal in the Signals List, and then in the Properties Window, you can select the IOS from the drop-down list.

Note

PADS I/O Designer supports a default IOS. You can change the default IOS in the database settings. You must not leave the IOS field empty, with the exception of MGT signals, whose IOS field can be left empty.

 

The example in Figure 6-3 shows the bus PDATA[0:63] being assigned an I/O standard of LVCMOS25. The “25” indicates this is a 2.5 Volt signal and will require that the Bank supplies be set to 2.5 Volts typically using the VCCO pins.

Figure 6-3. Setting the I/O Standard

When a signal is assigned a specific voltage, the entire bank is affected and unused pins are changed to the same I/O standard. A conflicting voltage level or I/O standard cannot be applied to that bank. As part of the I/O Standard assignment, PADS I/O Designer will also manage the power assignment for any affected banks. PADS I/O Designer creates a new power signal for the voltage and assigns it to the VCCO pins on the affected banks. In this example, the signal name would be V_2_5, but you can configure the signal names from Setup > Settings + PCB Signal Generation, as described in “PCB Signals Generation”.

Signal Locking

Locking signals is useful when multiple designers are sharing a database, or when you want to apply security to a signal. PADS I/O Designer does not allow you to delete, change the pin assignment, or change any other attribute of a locked signal. The Signal locking feature does not depend on any source control system. The locked/unlocked state of a signal is stored in the database.

Note

Locking signals does not prevent the import of a new signal definition, such as from HDL, from removing a signal.

 

To lock a signal or signal selection, right-click on it in the Signals List, and choose Lock Signals.

To unlock a signal or signal selection, right-click on it in the Signals List, and choose Unlock Signals.

A small padlock icon in the pin/signal list identifies locked signals.

Pin Locking

Locking pins is useful when multiple designers are sharing a database, and when you want to apply security to a pin. PADS I/O Designer does not allow you to change the pin assignment or any other attribute of a locked pin. The Pin locking feature does not depend on any source control system. The locked/unlocked state of a pin is stored in the database.

To lock a pin or pin selection, right-click on it in the Pins List, and choose Lock Pins.

To unlock a pin or pin selection, right-click on it in the Pins List, and choose Unlock Pins.

A small padlock icon in the pin/signal list identifies locked pins.