Importing I/O Signals Using HDL

PADS I/O Designer includes integrated VHDL, Verilog, EDIF and XML parsers. The following procedure describes how to import I/O signals into a database from source files in those formats using the Database Properties Dialog Box:

1. Select File > Database Properties to display the Database Properties Dialog Box.

2. Select the Signals source page.

3. Select VHDL or Verilog.

4. Specify the path to the file in the File path field. You can enter the path manually, or click Browse to navigate to the file’s location.

5. Go to the VHDL definition page.

6. Select the required entity, module or cell in the Entity dropdown box.

(Optional step) If appropriate, specify additional VHDL file(s) or Verilog search path(s) in the box below. See "Additional HDL Files" for more information.

7. Click OK.

8. Open the Synchronization Wizard.

9. Click Next and Finish on the Synchronization Wizard to import the data from the specified file.

The Signals List will be populated with the signals read from the source file.

Note
	If the file contains errors that prevent the signals from being read, then the errors found by the integrated parser are displayed. To continue reading in signals from the file, the errors have to be corrected first.

Additional HDL Files

Before the file containing the entity declaration is analyzed, it is sometimes necessary to analyze additional files in advance. This may be the case if, for example, the selected HDL file uses some constants declared in packages. PADS I/O Designer allows parsing any number of additional HDL files before the main one.

The VHDL definition page on the Database Properties Dialog Box contains the list of these additional HDL files.

1. To add a file to the list, use the Add File button located on the right side of the list.

2. To remove a file from the list, use the Remove Selected button.

3. Files are processed in the same order as presented on the list. To move a file up or down the list, click on it, and use the Move Up or Move Down button.

Since PADS I/O Designer installation already includes standard VHDL libraries (IEEE and STANDARD), there is no need to manually add these files for analysis.

Note that the main VHDL file is analyzed at the very end, after all of the additional files have been analyzed. So for example, if you have multiple entity architectures in separate files, the architecture that you want to use in PADS I/O Designer needs to be analyzed at the very end. To do this, you need to set the architecture file as the main file.

HDL Names and PCB Names

In the Signals List, each signal has an HDL Name and PCB Name. Upon loading an HDL netlist, both names assume the HDL name. The PCB Name can be used as the pin name during symbol creation by specifying Signal Name as the Port label for the PCB symbol in the Symbols Generator.

PCB names and HDL names can be changed by doing one of the following:

• Select the signal in the Signals List and edit the PCB Name or HDL Name fields in the Properties Window. DIFF children are also renamed.

• Right-click in the Signals List and select rename. A dialog appears into which the new PCB name and/or HDL name can be entered.

A checkbox can be used to select whether DIFF children are also renamed.

Changing the PCB name of a signal only affects the PCB names of its children. Similarly, changing the HDL name of a signal only affects the HDL names of its children.