It is recommended that you check the I/O design against any of the violations mentioned above by running it through the FPGA vendor tools before proceeding to the PCB process. PADS I/O Designer offers two ways to achieve these checks:
Note
PADS I/O Designer DRC supports Altera, but does not work with Xilinx.
After generating the Place and Route constraints, file the DRC utility from the chosen FPGA vendor can be run from within PADS I/O Designer through the Tools > Design Rule Check menu. This ensures that the design is not violating any of the I/O design rules.
When the Place and Route constraints file has been generated, continue the regular FPGA process by taking the design including the Place and Route constraints file through the FPGA vendor tool flow to implement the device. This way the design can be verified against any risks of not being able to implement the design.
Note
In both steps, the chosen FPGA vendor tools have to be installed in order to complete the checks.