Vendor Library Updates

In the case where these mechanisms fail to deliver the complete set of data, a request for more data will be discussed with the appropriate FPGA vendor through the partnership channel that Mentor Graphics has with all supported FPGA vendors. In some cases this data can be delivered quickly, while in other cases it takes some time for the FPGA vendors to make this data available.

Since the PADS I/O Designer device library has a one-to-one relationship with the same version of the FPGA vendor tool, any errors that were introduced in the FPGA vendor library will also exist in the PADS I/O Designer library unless they were found during the translation process. As soon as the FPGA vendor fixes their errors they will automatically make their way into the PADS I/O Designer device libraries. This could be as soon as the FPGA vendor releases their new software since Mentor Graphics is planning to make separate library updates for the PADS I/O Designer device libraries available through SupportNet more frequently than the major software releases.

PADS I/O Designer cannot guarantee that after changes have been made to the pin assignment the design:

• Is still routable due to the available FPGA surface given the new re-located signals. For example it could be difficult to route an FPGA for which 90% of the surface is used with a pin assignment that is not optimal for routability.

• Meets their timing requirements since the pin assignment also influences the timing paths and therefore the actual timing. So when a design is timing critical it could be that a new pin assignment will violate certain timing requirements.

• Meets all the I/O Design rules. The PADS I/O Designer built-in library with device and rule information is used on-the-fly to test the design. However, Mentor Graphics is dependent on the FPGA vendors for these rules and in some cases it takes time before the data becomes available.