Vendor Support Information

Pin numbers, pin names, pin function description for all device pins

Yes

Yes

Yes

Yes

Pin I/O bank number for assignable I/O pins and for Vcco, Vref, and other I/O bank dedicated power or ground pins

Yes

Yes

Yes

Yes

IO Banking Rules: Output standards with the same output VCCO requirement can be combined in the same bank

Yes

Yes

Yes

Yes

IO Banking Rules: Input standards with the same input VCCO and input VREF requirements can be combined in the same bank

Yes

Yes

Yes

Yes

IO Banking Rules: Input standards and output standards with the same input VCCO requirements can be combined in the same bank

Yes

Yes

Yes

Yes

IO Banking Rules: When combining bi-directional I/O with other standards, make sure the bi-directional standard can meet rules 1 through 3 above

Yes

Yes

Yes

Yes

IO Banking Rules: No more than one single termination type (input or output) is allowed in the same bank.

Yes

N/A

N/A

N/A

IO Banking Rules: No more than one split termination type (input or output) is allowed in the same bank.

Yes

N/A

N/A

N/A

IO Banking Rules: The placement of single-ended I/O pins with respect to LVDS I/O pins is restricted as detailed in “Design for Multiple Devices in a Common Package”.

N/A

Yes

N/A

N/A

Check swap group names. It is not allowed to assign signal to a pin if swap groups are different.

Yes

Yes

Yes

Yes

Check if type of signal and pin are the same. It is possible to force assignment in this case.

Yes

Yes

Yes

Yes

Recognize differential pin pairs; differential pins that belong together

Yes

Yes

Yes

Yes

Recognize differential signals, set a diff type for them and assign to diff pin pairs

Yes

Yes

Yes

Yes

Pin properties: available sink/source current levels for each I/O pin based upon selected I/O standard

Yes

Yes

Yes

Yes

SSO (WASSO) check for some families - based on vendor specific data and rules for SSO (WASSO)

Yes

No

No

No

Multiple sets of IO standards per family. If some pins have a smaller set of IO standards available, we are not able to prevent users from choosing a wrong IO standard for that pin. Therefore, we do not cover Low Capacitance (LC) check for pins.

Yes

Yes

Yes

No

Check direction when signal is assigned.

Yes

Yes

Yes

Yes

Special or additional types for Local Clock pins.

Yes

N/A

N/A

N/A

Ability to parse HDL code to recognize MGT channel pins. MGT types must be set for signals manually, before automatic assignment.

No

No

N/A

N/A

Interior cell information. Position of pads internally to a device.

No

Yes

No

No

VREF regions.

No

No

No

No

Checks that open drain is turned off for all pins with a differential I/O standard

?

No

?

?

Checks to see if the drive strength assignments are within the specifications of the I/O standard

Yes

Yes

Yes

Yes

Checks to see if the pin location supports the assigned drive path

N/A

No

N/A

N/A

Checks if the pin location supports BUSHOLD (dedicated clock pins do not support BUSHOLD)

N/A

Yes

N/A

N/A

Checks if the pin location supports WEAK_PULLUP (dedicated clock pins do not support WEAK_PULLUP)

N/A

Yes

N/A

N/A

Checks if the combined drive strength of consecutive pads does not exceed a certain limit

N/A

No

N/A

N/A

Checks if the pin location along with the I/O standard assigned support PCI_IO clamp dIODe

N/A

No

N/A

N/A

Checks if pins connected to PLL are assigned to the dedicated PLL pin locations

N/A

No

N/A

N/A

Checks that no single-ended I/O pin exists in the same bank as a DPA

N/A

No

N/A

N/A

Checks if single-ended output pins are a certain distance away from a differential I/O pin

N/A

Yes

N/A

N/A

Checks if single-ended output pins are a certain distance away from a VREF pad

N/A

Yes

N/A

N/A

Checks if single-ended input pins are a certain distance away from a differential I/O pin.

N/A

Yes

N/A

N/A

Checks that there are no more than a certain number of outputs or bidirectional pins in a VREFGROUP when a VREF is used

N/A

Yes

N/A

N/A

Checks if too many outputs are in a VREFGROUP

N/A

Yes

N/A

N/A

Set any IO pin as a VREF for > 128 macrocells Coolrunner II devices

No

N/A

N/A

N/A

Support for PROHIBIT constraint

No

N/A

N/A

N/A

Timing closure support (see the next 4 points)

No

Yes

Yes

Yes

a) Supported sources of actual times

*.twr

*.rpt

*.twr

N/A

b) Support constraint files as a source/destination

*.ucf

*.qsf

*.lcf, *.prf

N/A

c) Support for Constraint Manager

No

No

No

N/A

d) Support for synthesis constraint files

No

No

No

N/A