Banking rules: I/O banking restrictions based on VCCIO VREF for I/O standards.
Check if type of signal and pin are the same.
Check to see if the drive strength assignment is within the specifications of the I/O standard.
Multiple sets of I/O standards per family. Some pins have a smaller set of I/O standards available.
Example C-1.
Xilinx Assignment Rule
The following packages do not support DC1 in Banks 1 and 2: SF363, FF668, FF676, FF672, and FF1152.
The following devices do not support DC1 in Banks 1 and 2: XC4VLX15, XC4VLX25, XC4VSX25, XC4VSX35, XC4VFX12, XC4VFX20, XC4VFX40, AND XC4VFX60
When the clock-capable I/Os are driven by single-ended clocks, then the clock must be connected to the positive (P) side of the differential “clock capable” pin pair. The negative (N) side can be used as a general purpose I/O or left unconnected (Virtex4 Virtex5).
Virtex-4 has I/Os which cannot support differential output IO standards (identified in package files - *_LC_*).
Some pins of devices can be used only as inputs (e.g., pin name:”IP_x”) - Spartan3A.
An IOB cannot be configured to be both an input and an output if BIDIR ALLOWED is FALSE. The BIDIR_ALLOWED attribute is already available for IO standards and should be used in this case to block assignments of bidirections signals, if needed.
Note
The Xilinx Zynq family uses two types of pins: normal I/O pins that you can configure in PADS I/O Designer, and processor pins connected to an MIO interface that are dedicated and are not configurable in PADS I/O Designer. You can use the processor pins, but if processor pin assignments are exported to the constraint file (.ucf) and then imported to Xilinx ISE, an error occurs. To avoid the error, you should delete the processor pin entries in the constraint file manually, before importing the constraint file to Xilinx ISE.