I/O Pin Placement with Respect to LVDS I/O Pins

For the Altera Stratix III family, the placement of single-ended I/O pins with respect to LVDS I/O pins is restricted. As shown in Figure C-1, row I/O single-ended outputs with driving strength equal to or greater than 8 mA must be placed at least one row away from the LVDS I/O. The same restriction applies to single-ended inputs with OCT RT. You can place single-ended outputs with driving strength less than 8 mA in the rows adjacent to the LVDS I/O. The restriction does not apply when you use the LVDS input buffer for differential HSTL/SSTL input. Single-ended inputs without OCT RT have no placement restriction. When DPA is enabled, the constraint on single-ended I/O is the same as that on regular LVDS I/O.

Figure C-1. Single-Ended Row I/O Pin Placement for LVDS I/O Pins

The restriction on placing single-ended column I/O is similar to that on row I/O. Single-ended outputs with drive strength equal to or greater than 8 mA must be placed at least four I/Os away from the LVDS I/O. The same rule applies to single-ended input with OCT RT. The restriction does not apply when the LVDS input buffer is used for differential HSTL/SSTL inputs. Single-ended outputs with a driving strength less than 8 mA and single-ended inputs without OCT RT have no restriction. Figure C-2 shows the single-ended I/O placement rules for column I/O.

Figure C-2. Single-Ended Column I/O Pin Placement for LVDS I/O Pins